(1) Field of the Invention
The present invetion relates to a process for fabricating an integrated circuit device, which includes planarizing steps, such as bulk steps because of electrodes, element isolations, etc. or other steps such as wiring steps.
(2) Description of the Related Art
As the integration and miniaturization of intergrated circuit devices such as semiconductor intergrated circuit progress, the formation of fine multi-layer wiring layers are required on the surface of the intergrated circuit devices and as much planarization of the bulk steps underlying the multi-layer wiring layers as possible is desired. The term "bulk step" used here means steps formed on the surface of an intergrated circuit device, for example, by polysilicon electrodes or by element isolations of LOCOS oxides, etc., before the formation of metal wiring layers.
Although a high temperature treatment at a temperature higher than 550.degree. C. can be applied before the formation of metal layers, such a high temperature treatment cannot be used after the formation of a metal layer, e.g., an aluminum layer, since the metal wiring layer may be oxidized or fused.
To meet with the above demands, inorganic SOG (spin on glass) processes, organic SOG (spin on glass) processes, reflow processes of BPSG (borophosphosilicate glass) or other processes for planarization are utilized to fill or planarize steps including the bulk steps or other steps formed after bulk formation by metal wiring layers or the like.
Nevertheless, it is difficult to effectively reduce the above bulk steps by conventional planalization processes.
In the inorganic SOG process, it is difficult to form a thick layer without cracks. Accordingly, planalization of large steps is impossible, because in the inorganic SOG process, tetrasianol Si(OH).sub.4 is dehydration condensed to form (--SiO.sub.2 --).sub.n, during which the volume of the coated SOG layer is reduced significantly and, if the layer is thick, cracks are formed.
In the organic SOG process, a reduction of the volume of the layer is less or the volume is increased during the condensation of an organic silanol because organic groups remain. Accordingly, it is possible to form a thick layer without cracks. Nevertheless, the organic SOG layer is not heat resistant and therefore cannot be used for a bulk involving a high temperature treatment, particularly above 550.degree. C. If a device is heat treated, particularly at a temperature above 550.degree. C., after the organic SOG layer is made, the organic groups leave the layer and pores appear.
In the reflow process using BPSG, the reflowing a high purity BPSG requires a high temperature treatment of at least 850.degree. C., at which temperature borons introduced in a semiconductor substrate move to vary the doped impurity distribution and cause damage to a shallow junction, etc. Accordingly, the utilization of this reflow process is limited.
Further, a combination of an inorganic SOG layer and an underlying PSG (phospho-silicate glass) or BPSG layer and a combination of an inorganic SOG layer with an underlying CVD-SiO.sub.2 layer and a top PSG layer, so as to obtain a thick insulating layer are known. Nevertheless, in these combinations, the degree of planarization is insufficient because the inorganic SOG layer acting as the main planarizing layer is thin. Furthermore, these processes are complex and are low in productivity.
Therefore, the object of the present invention is to provive a process for planarizing an integrated circuit device which allows effective planarization of bulk steps derived from electrodes, element isolations, etc. and other steps derived from metal wiring layers, etc.